| Title |
The NAND Type Flash EEPROM using the Scaled SCNOSFET |
| Authors |
김주연(Kim, Ju-Yeon) ; 김병철(Kim, Byeong-Cheol) ; 김선주(Kim, Seon-Ju) ; 서광열(Seo, Gwang-Yeol) |
| Keywords |
SONOSFET ; NAND Flash EEPROM ; memory cell ; SPICE parameter ; modified Fowler-Nordheim tunneling |
| Abstract |
The SNOSFET memory devices with ultrathin ONO(tunnel oxide-nitride-blocking oxide) gate dielectric were fabricated using n-well CMOS process and investigated its characteristics. The thicknesses of tunnel oxide, nitride and blocking oxide were 23{ AA}, 53{ AA} and 33{ AA}, respectively. Auger analysis shows that the ONO layer is made up of SiO_2(upper layer of blocking oxide)/O-rich SiO_x N _y. It clearly shows that the converting layer with SiO_x N _y(lower layer of blocking oxide)/N-rich SiO_x N _y(nitride)/O-rich SiO_x N _y(tunnel oxide). It clearly shows that the converting layer with SiO_x N _y phase exists near the interface between the blocking oxide and nitride. The programming condition of +8 V, 20 ms, -8 V, 50 ms is determined and data retention over 10 years is obtained. Under the condition of 8 V programming, it was confirmed that the modified Fowler-Nordheim tunneling id dominant charge transport mechanism. The programmed threshold voltage is distributed less than 0.1 V so that the reading error of memory stated can be minimized. An 8×8 NAND type flash EEPROM with SONOSFET memory cell was designed and simulated with the extracted SPICE parameters. The sufficient read cell current was obtained and the upper limit of V_{TH} for write state was over 2V. |