| Title |
Dynamic Voltage Margin of AC PDP with the Narrow Erase Pulse Method |
| Authors |
안양기(An, Yang-Ki) ; 윤동한(Yoon, Dong-Han) |
| Keywords |
PDP ; Narrow erase ; Wall charge ; Margin ; Cell |
| Abstract |
This paper proposes the new narrow erase method to erase wall charges formed in an AC plasma display panel (PDP) cell. In the proposed method, pulse timing of switch at the sustain period is adjusted for inducing, a weak discharge. Then, after the narrow erase, the voltage of the X electrode is set to differ from that of the Y electrode. For the proposed method, the measured maximum address voltage margin was 38.3V at Y_Rest voltage of 100V and sustain voltage of 180~185V. However, for the conventional method, in which the X and Y electrodes are set to be of equal voltage after the narrow erase, the measured maximum address voltage margin was 31.3V at Y_Rest voltage of 150V and sustain voltage of 180V. This result shows that the measured maximum voltage margin for the proposed method is about 7V(22%) higher than that for the conventional method. |