| Title |
Acceleration Techniques for Cycle-Based Login Simulation |
| Authors |
박영호(Park, Young-Ho) ; 박은세(Park, Eun-Sei) |
| Keywords |
사이클 시뮬레이션 ; 회로분할 ; 병렬패턴 ; 게이트 감축기법 ; 시뮬레이션 가속화 ; |
| Abstract |
With increasing complexity of digital logic circuits, fast and accurate verification of functional behaviour becomes most critical bottleneck in meeting time-to-market requirement. This paper presents several techniques for accelerating a cycle-based logic simulation. The acceleration techniques include parallel pattern logic evaluation, circuit size reduction, and the partition of feedback loops in sequential circuits. Among all, the circuit size reduction plays a critical role in maximizing logic simulation speedup by reducing 50% of entire circuit nodes on the average. These techniques are incorporated into a levelized table-driven logic simulation system rather than a compiled-code simulation algorithm. Finally, experimental results are given to demonstrate the effectiveness of the proposed acceleration techniques. Experimental results show more than 27 times performance improvement over single pattern levelized logic simulation. |