| Title |
A 10bit 1MS/s 0.5mW SAR ADC with Double Sampling Technique |
| Authors |
이호규(Lee, Ho-Kyu) ; 김무영(Kim, Moo-Young) ; 김철우(Kim, Chul-Woo) |
| DOI |
https://doi.org/10.5370/KIEE.2011.60.2.325 |
| Keywords |
SAR ; ADC ; Data converter ; Double sampling ; 1MS/s ; 10b |
| Abstract |
This paper introduces the 10b 1MS/s SAR ADC with double sampling technique to reduce the power consumption. The SAR ADC is implemented in CMOS 1P8M 65nm technology and occupies 0.11um2. The maximum sampling rate is 1MS/s. The simulated SNDR and SFDR are 55.6dB and 62.7dB at 484kHz input frequency, respectively. The implemented data converter consumes 507uW with 1.2-V supply. |