| Title |
Design of Wide - range Clock and Data Recovery Circuit based Dual-loop DLL using 2-step DPC |
| Authors |
정기상(Jung, Ki-Sang) ; 김강직(Kim, Kang-Jik) ; 고귀한(Ko, Gui-Han) ; 조성익(Cho, Seong-Ik) |
| DOI |
https://doi.org/10.5370/KIEE.2012.61.2.324 |
| Keywords |
2-step DPC ; CDR ; Dual-loop ; High-speed interface |
| Abstract |
A recovered jitter of CDR(Clock and Data Recovery) Circuit based on Dual-loop DLL(Delay Locked Loop) for data recovery in high speed serial data communication is changed by depending on the input data and reference clock frequency. In this paper, 2-step DPC which has constant jitter performance for wide-range input frequency is proposed. The designed prototype 2-step CDR using proposed 2-step DPC has operation frequency between 200Mbps and 4Gbps. Average delay step of 2-step DPC is 10ps. Designed CDR circuit was tested with 0.18um CMOS process. |