| Title |
A Radiation-hardened Model Design of CMOS Digital Logic Circuit for Nuclear Power Plant IC and its Total Radiation Damage Analysis |
| Authors |
이민웅(Min-Woong Lee) ; 이남호(Nam-Ho Lee) ; 김종열(Jong-Yeol Kim) ; 조성익(Seong-Ik Cho) |
| DOI |
http://doi.org/10.5370/KIEE.2018.67.6.745 |
| Keywords |
Nuclear power plant ; Integrated circuit ; Total ionizing dose ; Radiation-hardening technology ; D-latch ; Unit cell |
| Abstract |
ICs(Integrated circuits) for nuclear power plant exposed to radiation environment occur malfunctions and data errors by the TID(Total ionizing dose) effects among radiation-damage phenomenons. In order to protect ICs from the TID effects, this paper proposes a radiation-hardening of the logic circuit(D-latch) which used for the data synchronization and the clock division in the ICs design. The radiation-hardening technology in the logic device(NAND) that constitutes the proposed RH(Radiation-hardened) D-latch is structurally more advantageous than the conventional technologies in that it keeps the device characteristics of the commercial process. Because of this, the unit cell based design of the RH logic device is possible, which makes it easier to design RH ICs, including digital logic circuits, and reduce the time and cost required in RH circuit design. In this paper, we design and modeling the structure of RH D-latch based on commercial 0.35㎛ CMOS process using Silvaco's TCAD 3D tool. As a result of verifying the radiation characteristics by applying the radiation-damage M&S (Modeling&Simulation) technique, we have confirmed the radiation-damage of the standard D-latch and the RH performance of the proposed D-latch by the TID effects. |