| Title |
Study of the Method to Minimize Switching Loss by Individual Control of Parallel Switches |
| Authors |
김재헌(Jae-Heon Kim) ; 임성환(Seong-Hwan Im) ; 구본관(Bon-Gwan Gu) |
| DOI |
https://doi.org/10.5370/KIEE.2021.70.5.750 |
| Keywords |
Inverter; Power semiconductor; Parallel connection; Switching losses; Switching pattern; Efficiency |
| Abstract |
Generally, high-power inverters are composed of power semiconductors connected in parallel such as an IGBT. The simplest way to control semiconductors connected in parallel is to control all switches with the same switching sequence. However, this control method can cause high switching losses in all switches and imbalance in life among switches. This paper proposes switching patterns that minimize switching losses by individual control of the switches. Different switching losses are calculated depending on the switching pattern and compared by experiment. Through this process, switching patterns that minimize losses are analyzed.
Experimental results show that the overall inverter efficiency can be increased with the proposed method under the various current conditions. |