| Title |
Implementation and Performance Evaluation of TSMB Bus System with Time Synchronized Multiple Bi-Directional TMDS Data Transmissions for Intelligent Electronic Devices |
| Authors |
황병창(Byeung-Chang Hwang) ; 민병기(Byeung-Gi Min) ; 김동준(Dong-Joon Kim) ; 윤종호(Chong-Ho Yoon) |
| DOI |
https://doi.org/10.5370/KIEE.2023.72.1.37 |
| Keywords |
IED; TSMB bus; TMDS; FPGA; IEEE1588v2 PTP |
| Abstract |
In this paper, we propose a novel TSMB bus system with multiple bidirectional data transmission and time synchronization capability for IEDs(Intelligent Electronic Devices). Unlike the legacy unidirectional TMDS(Transition Minimized Differential Signaling) used for transfer digital video signals, the proposed bus system employs dual high-speed serial TMDS link for sending trigger signals from the FPGA of main processor module and receiving the sampled data from submodules such as either current or potential transformers. For simultaneous triggering multiple submdoules, we also employ the precision timing protocol processing capability in the main processor, which generates the wall clock pulse per second(PPS) synchronized to GPS. Adopting PLL for the PPS signal, we can provide the reference clock of 98.304MHz for supporting the data rate of 491.52 Mbps over each TMDS link.
The data rate can support eight 24 bits ADCs for PTs or CTs in the single link, each of which requires 4800 samplings per second.
An implemented TSMB bus system with FPGA consists of a single main processor with clock expander and eight submodules, in which each submodule is connected with the bidirectional TMDS link to the FPGA of main processor module. The jitter of 1 PPS between the two main processor modules was measured to be less than 102nsec at the maximum, and the jitter of the TSMB transmission data line was measured to be less than or equal to 660ps at the TP3 point of the receiving side, confirming that the TMDS specification was satisfied. Finally, the proposed time- synchronized multi-directional bus system can contribute to the improvement of the reliability and performance of the algorithm of the intelligent protection relay system through the optimal transmission of equivalent and simultaneous sampling data without the involvement of the processor. |