| Title |
The Design of Robust DSC-PLL under Distorted Grid Voltage Contained Unbalance on Frequency Variation |
| Authors |
이재도(Jae Do Lee) ; 차한주(Han Ju Cha) |
| DOI |
http://doi.org/10.5370/KIEE.2018.67.11.1447 |
| Keywords |
Delayed Signal Cancellation(DSC) ; Phase locked loop ; Interpolation method |
| Abstract |
In this paper, the design of robust DSC-PLL(Delayed Signal Cancellation Phase Locked Loop) is proposed for coping with frequency variation. This method shows significant performance for detection of fundamental positive sequence component voltage when the grid voltage is polluted by grid unbalance and frequency variation. The feedback frequency estimation of DSC-PLL is tracking the drift in the phase by unbalance and frequency variation. The robust DSC PLL is to present the analysis on method and performance under frequency variations. These compensation algorithms can correct for discrepancies of changing the frequency within maximum 193[ms] and improve traditional DSC-PLL. Linear interpolation method is adopted to reduce the discretized errors in the digital implementation of the PLL. For verification of robust characteristic, PLL methods are implemented on FPGA with a discrete fixed point based. The proposed method is validated by both Matlab/Simulink and experimental results based on FPGA(XC7Z030). |