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Trans. Korean. Inst. Elect. Eng.
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2018-11
(Vol.67 No.11)
10.5370/KIEE.2018.67.11.1447
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REF
References
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Huang Qicheng, Rajashekara Kaushik, 2017, An Improved Delayed Signal Cancellation PLL for Fast Grid Synchronization under Distorted and Unbalanced Grid Condition, IEEE Trans. on Industry Applications, Vol. 53, pp. 4985-4997
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Jo Jongmin, Han Byung-Moon, Cha Hanju, 2015, FPGA based DSC-PLL for grid harmonics and voltage unbalance effect elimination, 2015 IEEE Applied Power Electronics Conference and Exposition (APEC), pp. 2212-2216