| Title |
Wafer Map Defect Analysis Based on EfficientNetV2 using Grad-CAM 553 |
| Authors |
이한성(Han-sung Lee) ; 조현종(Hyun-chong Cho) |
| DOI |
https://doi.org/10.5370/KIEE.2023.72.4.553 |
| Keywords |
Defect analysis; Semiconductor; Deep learning; Grad-CAM |
| Abstract |
In semiconductors, various defect patterns appear on the wafer map due to problems in the design and manufacturing process.
Analysis of generated defect patterns will reduce the rate of defects and enable the production of high-quality semiconductors.
Considering the number of semiconductors produced, performing defect analysis by human resources is inefficient. Recently, as hardware performance has improved, high-performance deep learning models have been designed. These models show high performance in image classification and have advantages in terms of processing speed. Therefore, this paper used EfficientNetV2 designed to achieve maximum efficiency with few parameters for semiconductor failure analysis. Identifying the location of defects is a critical element of defect analysis, not just classifying defect patterns. Therefore, in this study, we used Grad-CAM to identify the classification of defect patterns and their approximate location. Wafer map dataset is difficult to collect as data includes defects in manufacturing companies' processes. To train EfficientNetV2, we used the WM-811K dataset, a publicly available dataset on Kaggle. This dataset has an imbalance in the number of data between classes. We increased the data using Flip and Rotate to address the dataset's imbalances, ultimately improving the classification performance. The test results showed an accuracy of 0.944 and an F1-score of 0.929. |