1. Introduction

The global development in industrialization increases energy consumption, resulting in the continued usage of fossil fuels. Rising carbon dioxide emissions from the combustion of fossil fuels have accelerated global warming, causing major environmental concerns. Electricity generated from renewable energy sources like photovoltaic (PV), wind, or biomass might take the place of fossil fuel-based electricity generation. The design of a grid-connected converter, as depicted in fig 1, is critical for such systems because it supplies stable AC power to the grid and loads from the DC power of the renewable energy source.

The constant expansion of the power electronic system, which has led to a rise in the demand for electricity, has placed a heavy emphasis on system operations and control. Thanks to thorough research and developments in circuit structures, control algorithm, semiconductor devices, passive components, and system integration techniques, the efficiency and power density of power electronic systems have been continuously enhanced.

Current applications of power electronics devices require large redundancies for device reliability issues. At the component level, capacitors and semiconductor switching devices [e.g., IGBTs, SiC MOSFET] are the two categories of reliability- critical components. The conducted survey demonstrates that capacitor and semiconductor devices are the most vulnerable component ⁽¹⁾, ⁽²⁾. The three significant factors, that having both direct and indirect influences on the failure of power components, are high temperature, vibaration, and moisture. Common causes of capacitor deterioration are high temperature, high humidity, and severe current. It reduces capacitance and increases equivalent series resistance (ESR) ⁽³⁾, ⁽⁴⁾. When capacitance is decreased, the voltage fluctuation of the capacitor will increase. And the increase in ESR will cause the temperature to rise, which will accelerate the aging of the capacitor in a vicious circle. Regarding semiconductor devices, during long-term operations under high-temperature stresses, SiC MOSFET switches are gradually degraded and eventually worn out. Numerous previous study results indicate that junction temperature increases as thermal resistance increases, resulting in an increase in on-state resistance ⁽⁵⁾, ⁽⁶⁾.

In industry and academics, multilevel converters are gaining popularity as one of the main solutions of electronic power conversion for high-power applications. In this sense, multilevel converters have a structure that allows a better distribution of voltages in switches and the ability to synthesize more sine-shaped voltages. Among various multilevel topologies modular multilevel converter (MMC) is one of the most outstanding structure with modular and scalable characteristics, and excellent quality output ⁽⁷⁾, ⁽⁸⁾. MMCs use full-bridge or half-bridge cells to form a series of connected submodules (SMs) in each leg, which allows more considerable flexibility over other topologies. Even though it is a valuable and proven technology, multilevel converters present plenty of challenges since the use of numerous capacitors and semiconductor switching devices. The long-term device degradations in capacitors and semiconductor devices can exert negative impact on the power converter performance.

Fig. 1. Three-phase MMC configuration.

2. Modular multilevel converter

fig 1displays the typical arrangement of a three-phase MMC with two arms constituting one phase of the converter. Each arm is connected with an inductor $L_{a}$ to restrict the current caused by the arm’s instantaneous voltage variations. One arm is composed of $N$ half-bridge SMs, which are the most basic cells of an MMC. $SM_{ujx}(j=1,\:...,\: N; x = a,\:b,\:c)$ stands for SM in the upper arm, whereas $SM_{ljx}(j=1,\:...,\: N; x = a,\:b,\:c)$ indicates SM in the lower arm. The half-bridge SM is in charge of generating zero and positive voltages, which correspond to the switching states of the upper and lower switches $S_{1}$ and $S_{2}$. The SMs can be switched in two distinct ways: the “inserted” state, defined as when $S_{1}$ is ON and $S_{2}$ is OFF, and the “bypassed” state, defined as when $S_{1}$ is OFF and $S_{2}$ is ON. Consequently, the phase-$x(x = a,\:b,\:c)$ output voltage of the MMC can include maximum $2N+1$ voltage levels, varying between $-V_{dc}/2$ and $+V_{dc}/2$.

A PSC-PWM control scheme in ⁽⁹⁾ is used to operate the three-phase MMC. The control scheme includes two seperate control loops referred as the averaging loop and the balancing loop. The averaging control loop ensures the average value of SM capacitor voltage by controlling the circulating current. Meanwhile, the balancing control loop maintains the balance of the capacitor voltage among SMs of the MMC.

3. Investigation of aging devices impact result

The investigation of aging devices impact on the MMC performance is implemented using PSIM simulation program. The simulation parameters of three-phase MMC is shown in table 1. Additionally, fig 2presents the experimental setup of a single-phase seven-level MMC, which will be used to verify the correctness of control algorithm.

Fig. 2. Experimental setup of single-phase seven-level MMC.

Fig. 3. (a) Simulation result of seven-level three-phase MMC, (b) Experimental result of seven-level single-phase MMC.

3.1 Aging capacitor

The impact of aging capacitor voltage on MMC is investigated by reducing the corresponding capacitance of SM capacitance by 10% to 50%. The SM capacitor voltage, output currents, and circulating currents performance will be compared with the healthy condition to evaluate the influence of the aging capacitor. The rate of charging and discharging capacitor voltage will increase because the reduction in capacitance induced by aging. It indicates that the variation of the related capacitor voltage will be more significant than remaining SMs. Consequently, this can result in an increase in SM capacitor voltage ripple and unequal power distribution among the SMs in the arm.

Fig. 4. (a) Simulation result of seven-level three-phase MMC following the reduction of capacitance in phase a (a) The capacitance of reduces by 10%, (b) The capacitance of reduces by 20%, (c) The capacitance of reduces by 30%, (d) The capacitance of reduces by 40%

fig 4shows the simulated results of the seven-level three-phase MMC in the case of an aging capacitor that the phase a capacitance of $SM_{u1a}$decreases by from 10% to 40%. As shown in fig 4(a) - (d), the output currents are sinusoidal and precise in terms of magnitude and phase. The phase output voltage contains correctly seven levels, which varying from $-V_{dc}/2$ to $V_{dc}/2$. In terms of capacitor voltage balancing, fig 4shows the SM capacitor voltage waveforms in only phase a to clarify the change of capacitor voltage. It can be seen that in fig 4(a) - (d), the SM capacitor voltage $v_{Cu1a}$ has a higher ripple than the remaining SM capacitor voltage. The SM capacitor voltage $v_{Cu1a}$ripple increases following the reduction of corresponding capacitance. The balance of SM capacitor voltage between upper and lower arms decreases following the reduction of capacitance, as shown in fig 4. Due to the increase of SM capacitor voltage ripple, the corresponding circulating current increases as well. The peak-to-peak value of phase a circulating current increases following the reduction of capacitance.

Fig. 5. (a) Simulation result of seven-level three-phase MMC (a) The capacitance of reduces by 50%, (b) The capacitance of reduces by 50%, (b) The capacitance of reduces by 50%, (d) The capacitance of reduces by 50%

fig 5(a) and (b) show the simulated results of the seven-level three-phase MMC in the case of an aging capacitor that the phase a capacitance of $SM_{u1a}$ and capacitance of $SM_{l1a}$ decrease by 50%. It can be seen that the output currents are sinusoidal and precise in terms of magnitude and phase. The phase output voltage contains correctly seven levels, which varying from $-V_{dc}/2$ to $V_{dc}/2$. In terms of capacitor voltage balancing, fig 5(a) and (b) show only the SM capacitor voltage waveforms in only phase a to clarify the change of capacitor voltage. It can be seen that in fig 5(a), the SM capacitor voltage $v_{Cu1a}$ has a higher ripple than the remaining SM capacitor voltage. The corresponding peak-to-peak value increases to 18.19V, which is equivalent to a 108.6% of increment from the healthy condition. Meanwhile, as in fig 5(b), the SM capacitor voltage $v_{Cl1a}$ the peak-to-peak value increases to 18.42V, equivalent to a 111.2% of increment. Additionally, it can be noticed from both fig 5(a) and (b) the SM capacitor voltages in the upper and lower arms of phase a are not kept balanced well. In the remaining phase legs, the SM capacitor voltage in the upper and lower arms are almost unchanged and kept balanced at the nominal value $V_{dc}/N$. Due to the increase of SM capacitor voltage ripple, the corresponding circulating current increases as well. In fig 5(a) and (b), the circulating current of phase a has higher ripples, leading to the increased RMS value at 4.04A, whereas the circulating current RMS value of phase b and c is 3.74A. fig 5(c) and (d) present the simulated results of the seven-level three-phase MMC in the case of an aging capacitor that the phase b capacitance of $SM_{u1b}$ and phase c capacitance of $SM_{u1c}$ decrease by 50%. Similar to fig 5(a) and (b), the reduction of capacitance of $SM_{u1b}$and $SM_{u1c}$ result in the same impact on the output performance. The output currents and voltages are precise in terms of magnitude and phase. The SM capacitor voltages $v_{Cu1b}$ and $v_{Cu1c}$ have higher ripple than remaining SM capacitor voltages. Additionally, the corresponding phase b and c circulating currents increases as shown in fig 5(c) and (d), respectively.

Fig. 6. The change of SM capacitor voltage peak-to-peak value following the reduction of capacitance in phase a. (a) The capacitance of reduces, (b) The capacitance of reduces, (c) The capacitance of different SMs reduces.

fig. 6(a) and (b) present the change of SM capacitor voltage peak-to-peak values following the reduction of capacitance in phase a of MMC. Apparently, when the aging condition occurs in one SM of phase a, the corresponding SM capacitor voltage peak-to-peak value increases following the reduction of capacitance. As shown in fig. 6(a), capacitance of $SM_{u1a}$ decreases, the corresponding SM capacitor voltage peak-to-peak value increases by 108.6% when the capacitance reduction is 50%. The remaining SM capacitor peak-to-peak values in phase a increase from 1 – 12%. Meanwhile, the SM capacitor voltage peak-to-peak values in phase b and phase c are almost unchanged, and the increase is negligible at about 1%. When the aging capacitor occurs in $SM_{l1a}$, the corresponding SM capacitor voltage peak-to-peak value increases as presented in fig. 6(b). In fig. 6(c), the change of capacitor voltage peak-to-peak value is presented when different SMs capacitance in phase a decreases by 50%. It can be seen that the corresponding SM capacitor voltage peak-to-peak value increases by about 110%. The remaining SM capacitor peak-to-peak values in phase a slightly increase from 1 to 12%.

Fig. 7. The change of output current THD following the reduction of capacitance in phase a. (a) The capacitance of reduces, (b) The capacitance of reduces, (c) The capacitance of different SMs reduces.

fig 5(a) and (b) show the change of output current THDs following the reduction of capacitance in phase a of MMC. Apparently, the output current THD increases following the reduction of corresponding capacitance. As presented in fig 7(a), capacitance of $SM_{u1a}$ decreases, the phase a output current increases by 118% when the capacitance reduction is 50%. The phase b and c output current THDs increase by 41% and 36%, respectively. In fig 7(b), capacitance of $SM_{l1a}$ decreases, the phase a output current increases by 95% when the capacitance reduction is 50%. The phase b and c output current THDs increase by 33% and 28%, respectively. It can be noticed that the reduction of capacitance in upper arm SMs has a higher impact on the output current THD than that of lower arm SMs. This is presented in fig 7(c), where the capacitance of different SMs in phase a decreases by 50%. The output current THDs during the reduction of capacitance in upper arm SMs are higher than that of lower arm SMs, about 8% to 20%.

Regarding the circulating current performance, fig 5(a) and (b) show the change in circulating current RMS value following the reduction of capacitance at $SM_{u1a}$ and $SM_{l1a}$, respectively. The reduction of capacitance in upper and lower arm SMs has the same impact on the corresponding phase circulating current. When the capacitance reduces by 50%, the corresponding circulating current increase by 8.3%, while the remaining circulating currents negligibly rise by 0.3%. This change is similar to both three phase legs of MMC.

3.2 Aging switch

The impact of an aging MOSFET switch on the seven-level three-phase MMC is investigated by increasing the corresponding on-state resistance $R_{ds}$ by two to ten times. The SM capacitor voltage, output currents, and circulating currents performance will be compared with the healthy condition to evaluate the influence of the aging capacitor. As indicated in fig 1, the half-bridge SM includes upper and lower switches. The impact of aging MOSFET switch is investigated for both upper and lower switches.

Fig. 9. Simulation result of seven-level three-phase MMC (a) Upper switch on-state resistance increases by ten times, (b) Lower switch. on-state resistance increases by ten times.

The simulation waveforms of the seven-level three-phase MMC in the case of an aging switch that the on-state resistance $R_{ds}$ of upper and lower switches in $SM_{u1a}$ increases ten times are presented in fig 5(a) and (b), respectively. It can be realized that the difference between healthy conditions and aging switch condition is not noticeable. The output currents are sinusoidal and accurate in terms of phase and magnitude. The phase output voltage contains correctly seven levels, which varying from $-V_{dc}/2$ to $V_{dc}/2$. However, in fig 9(a), the phase a output current THD is 0.46%, which is 18% higher than that of healthy condition. Meanwhile, the phase a output current THD in fig 9(b) is 0.79%. The SM capacitor voltages in both upper and lower arms among three phase legs are kept balanced at the nominal voltage $V_{dc}/N$. The change of SM capacitor voltage peak-to-peak value is about 1 to 3%. Regarding the circulating currents, both three phase circulating currents are unchanged. The corresponding RMS value is kept at 3.73A.

Fig. 10. The change of output current THD following the rise of on-state resistance (a) Upper switch, (b) Lower switch, (c) Different SM in phase a.

By observing the simulation waveform of MMC in fig 10, it can see that the increase of $R_{ds}$ has negligible impact on the SM capacitor voltage and circulating current. However, the aging switch condition mainly exerts an influence on the output current THD. fig 10shows the change of output current THD following the change of on-state resistance. In fig 10(a), when the upper switch of $SM_{u1a}$ is aged, it leads to the increase of phase a output current following the rise of corresponding on-state resistance. When the on-state resistance increases ten times, the phase a output current THD increases by 18%, whereas the output current THD of phase b and c slightly increase by 3% and 5%, respectively. The increase of output current THD caused by a lower switch in $SM_{u1a}$ is significantly higher than that of the upper switch. As can be seen in fig 10(b), when the on-state resistance increases ten times, the phase a output current THD increases by 103% compared with the healthy condition. Meanwhile, phase b and c output current THDs also increase considerably by 31% and 33%, respectively. In order to confirm the influence of increased on-state resistance between upper and lower switches, fig 10(c) presents the change of output current THD caused by different switches in phase a. It can be noticed that the aging lower switch in SM has a higher impact on the output current THD than that of the aging upper switch. In the upper arm of phase a, the increased output current THD caused by the aging lower switch is about five times higher than that of the upper switch. On the other hand, in the lower arm of phase a, the increased output current THD caused by the aging lower switch is about ten times higher than that of the upper switch.

It can be concluded that in seven-level three-phase MMC, the reduction of SM capacitance due caused by aging capacitor has a substantial impact on both SM capacitor voltages, output current, and circulating current performance. The SM capacitor voltage peak-to-peak value, output current THD, and circulating current RMS value increase following the reduction of SM capacitance. Additionally, the aging SM capacitor affects the balancing controllability of upper and lower arm SM capacitor voltages. In terms of the aging switch, the increase of on-state resistance has a negligible impact on the SM capacitor voltage and circulating current. The change of SM capacitor voltage peak-to-peak value and circulating current RMS value is minor when the switch is aged. However, the increase of on-state resistance leads to the rise of corresponding output current THD. The increased output current THD caused by the aging lower switch is significantly higher than that of the upper switch in one SM.

4. Conclusion

This paper presents a complete result of the multilevel converter degradation performance under an aging capacitor and MOSFET switch. The capacitance variation in the aging capacitor and on-state resistance variation in the aging switch are investigated to evaluate the impact on multilevel converter performance. In MMC, the reduction of SM capacitance leads to the increase of SM capacitor voltage ripple and balancing controllability. Additionally, the aging capacitor and switch make the output current THD increase significantly.