Y. H. Loh, Y. S. Yang, 2012, Design of 100-V super- junction trench power MOSFET with low on-resistanc, ETRI Journal, Vol. 34, No. 1, pp. 134-137

Y. H. Ham, D. P. Kim, K. H. Baek, K. S. Park, K. H. Kwon, L. M. Do, 2012, Analysis of a metal filling and liner formation mechanism of the blind via with nano-Ag particles for TSV (through silicon via) interconnection, Journal of Micromechanics and Microengineering, 075013, Vol. 22, No. 7

J. S. Park, D. H. Kang, S. M. Kwak, T. S. Kim, J. H. Park, T. G. Kim, S. H. Baek, B. H. Lee, 2020, Low- temperature smoothing method of scalloped DRIE trench by post-dry etching process based on SF6 plasma, Micro and Nano Systems Letters, 14, Vol. 8, No. 1

J. K. Perng, 2006, High aspect-ratio nanoscale etching in silicon using electron beam lithography and deep reactive ion etching (DRIE) technique, Thesis, Georgia Institute of Technology

H. V. Jansen, M. J. de Boer, S. Unnikrishnan, M. C. Lou- werse, M. C. Elwenspoek, 2009, Black silicon method X: a review on high speed and selective plasma etching of silicon with profile control: an in-depth comparison between Bosch and cryostat DRIE processes as a roadmap to next generation equipment, Journal of Micromechanics and Microengineering, 033001, Vol. 19, No. 3

B. Wu, A. Kumar, S. Pamarthy, Journal of Applied Physics, 2010, High aspect ratio silicon etch: A review, 051101, Vol. 108

P. Dixit, J. Miao, 2006, Effect of SF6 flow rate on the etched surface profile and bottom grass formation in deep reactive ion etching process, Journal of Physics: Conference Serires, Vol. 34, pp. 577-582

B. K. Yu, M. Y. Kim, T. S. Oh, 2012, Anisotropic wet- etching process of Si substrate for formation of thermal vias in high-power LED packages, Journal of the Microelectronics and Packaging Society, Vol. 19, No. 4, pp. 51-56

Y. C. Hsin, C. C. Chen, J. H. Lau, P. J. Tzeng, S. H. Shen, Y. F. Hsu, S. C. Chen, C. Y. Wn, J. C. Chen, T. K. Ku, M. J. Kao, 2011, Effects of etch rate on scallop of through-silicon vias (TSVs) in 200mm and 300mm wafers, 2011 IEEE 61st Electronic Components and Technology Conference, pp. 1130-1135

S. P. Koirala, I. Awaah, S. L. Burkett, M. H. Gordon, 2011, Correlation of plasma characteristics to etch rate and via sidewall angle in a deep reactive ion etch system using Langmuir probe and optical emission spectroscopy, Journal of Vacuum Science & Technology A, 011008, Vol. vo. 29, No. 1

T. Rowbotham, J. Patel, T. Lam, I. U. Abhulimen, S. Burkett, L. Cai, L. Schaper, 2006, Back side exposure of variable size through silicon vias, Journal of Vacuum Science & Technology B, Vol. 24, No. no 5, pp. 2460-2466

M. K. Hooda, M. Wadhwa, S. Verma, M. M. Nayak, P. J. George, A. K. Paul, 2010, A systematic study of DRIE process for high aspect ratio microstructuring, Vacuum, Vol. 84, pp. 1142-1148

S. M. Choi, S. J. Hong, 2005, Use of hard mask for finer (<10 μm) through silicon vias (TSVs) etching, Transactions on Electrical and Electronic Materials, Vol. vo. 16, No. 6, pp. 312-316

D. L. Goldfarb, A. P. Mahorowala, G. M. Gallatin, K. E. Petrillo, K. Temple, M. Angelopoulos, 2004, Effect of thin- film imaging on line edge roughness transfer to under- layers during etch processes, Journal of Vacuum Science & Technology B, Vol. 22, No. 2, pp. 647-653

O. Joubert, P. Czuprynski, F. H. Bell, P. Berryyer, R. Blanc, 1997, Analyses of the chemical topography of silicon dioxide contact holes etched in a high density plasma source, Journal of Vacuum Science & Technology B, Vol. 15, No. 3, pp. 629-639

R. J. MacDonald, S. Goswami, R. Ruffalo, M. Edmond, C. Szymanski, 2021, Influence of resist profile on DRIE sidewall morphology, Advanced Semiconductor Manufacturing Conference (ASMC), 2021 32nd Annual SEMI, pp. 1-4

M. Oumura, J. Hashimoto, T. Adachi, Y. Kondo, M. Ishikawa, J. Abe, I. Sakai, H. Hayashi, M. Sekine, M. Hori, 2019, Formation mechanism of sidewall striation in high- aspect-ratio hole etching, Japanese Journal of Applied Physics, SEEB02, Vol. 58